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| www..com SPICE Device Model SUP/SUB70N03-09P Vishay Siliconix N-Channel 30-V (D-S), 175C MOSFET PWM Optimized CHARACTERISTICS * N-Channel Vertical DMOS * Macro Model (Model Subcircuit Schematic) * Level 3 MOS * Apply for both Linear and Switching Application * Accurate over the -55 to 125C Temperature Range * Model the Gate Charge, Transient, and Diode Reverse Recovery Characteristics DESCRIPTION The attached spice model describes the typical electrical characteristics of the n-channel vertical DMOS. The subcircuit model schematic is extracted and optimized over the -55 to 125C temperature ranges under the pulsed 0-to-5V gate drive. The saturated output impedance is best fit at the gate bias near the threshold voltage. A novel gate-to-drain feedback capacitance network is used to model the gate charge characteristics while avoiding convergence difficulties of the switched Cgd model. All model parameter values are optimized to provide a best fit to the measured electrical data and are not intended as an exact physical interpretation of the device. SUBCIRCUIT MODEL SCHEMATIC www..com This document is intended as a SPICE modeling guideline and does not constitute a commercial product data sheet. Designers should refer to the appropriate data sheet of the same number for guaranteed specification limits. Document Number: 71566 05-Nov-98 www.vishay.com 1 www. .com www..com SPICE Device Model SUP/ SUB70N03-09P Vishay Siliconix SPECIFICATIONS (TJ = 25C UNLESS OTHERWISE NOTED) Parameter Static Gate Threshold Voltage On-State Drain Current a Symbol VGS(th) ID(on) Test Conditions VDS = VGS, ID = 250 A VDS = 5 V, VGS = 10 V VGS = 10 V, ID = 30 A Typical 1.67 621 0.007 0.011 0.0108 0.0127 51 0.92 Unit V A Drain-Source On-State Resistance a rDS(on) VGS = 4.5 V, ID = 20 A VGS = 10 V, ID = 30 A, 125C VGS = 10 V, ID = 30 A, 175C Forward Transconductance Diode Forward Voltage a a gfs VSD VDS = 15 V, ID = 30 A IF = 70 A, VGS = 0 V S V Dynamic b Input Capacitance Output Capacitance Reverse Transfer Capacitance Total Gate Chargec Gate-Source Chargec Gate-Drain Chargec Turn-On Delay Timec Rise Timec Turn-Off Delay Timec Fall Time c Ciss Coss Crss Qg Qgs Qgd td(on) tr td(off) tf VDD = 15 V, RL = 0.21 ID 70 A, VGEN = 10 V, RG = 2.5 VDS = 15 V, VGS = 10 V, ID = 70 A VGS = 0 V, VDS = 25 V, f = 1 MHz 2681 664 310 46 8.5 11 13 11 35 ns nC pf Source-Drain Reverse Recovery Time www..com trr IF = A, di/dt = 100 A/s 12 35 Notes a. Pulse test; pulse width 300 s, duty cycle 2%. b. Guaranteed by design, not subject to production testing. c. Independent of operating temperature www.vishay.com 2 Document Number: 71566 05-Nov-98 www. .com www..com SPICE Device Model SUP/SUB70N03-09P Vishay Siliconix COMPARISON OF MODEL WITH MEASURED DATA (TJ=25C UNLESS OTHERWISE NOTED) www..com Document Number: 71566 05-Nov-98 www.vishay.com 3 www. .com |
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